Duplicate compact discs (CD-R""s) have been filed with the present application as a computer program listing appendix. Each compact disc contains the following file: xe2x80x9ccodexe2x80x9d (105 kB, created Jun. 19, 2003). The material on the compact discs is incorporated herein by reference as a computer program listing appendix.
The present invention generally relates to power integrity analysis in semiconductor layout, and more specifically relates to a graphic user interface which is configured to integrate third party tools in power integrity analysis.
As shown in FIG. 1, presently, when an engineer wants to design a semiconductor layout and then perform a transistor-level power integrity analysis of the layout, the engineer (user 10 in FIG. 1) first uses a design tool 12 to design the layout. Such design tools include Avant! and FlexStream. After the engineer has designed the layout, he or she inputs as much information as possible about the layout into a power integrity analysis integration tool 14, and uses the analysis tool to perform a transistor-level power integrity analysis of the layout. Depending on the results of the analysis, the engineer 10 may revise the layout using the design tool 12 and re-analyze the revised layout. The process may be repeated several times.
The present method of using one tool (a design tool) to design a semiconductor layout and manually entering information about the layout into another tool (an analysis tool) in order to perform a transistor-level power integrity analysis of the layout requires that data be entered twice. Hence, the method is tedious and is prone to error. Additionally, the method is inefficient due to the lack of batch queuing. The inputs are generally so fragmented into different setup files, etc. that it is extremely difficult to complete the flow in one attempt without experiencing setup file problems or errors. Furthermore, the method requires, as a result of having to make manual entries into the power integrity analysis integration tool, that the engineer effectively be an expert in running such power integrity tools.
A general object of an embodiment of the present invention is to provide a graphic user interface which is configured to integrate third party tools in power integrity analysis.
Another object of an embodiment of the present invention is to provide a graphic user interface which is configured to extract information about a semiconductor layout from a design tool which has been previously used to design the semiconductor layout.
Still another object of an embodiment of the present invention is to provide an integrated power integrity analysis flow suite which is efficient and relatively easy to use.
Still yet another object of an embodiment of the present invention is to provide a power integrity analysis method which is not prone to error.
Yet still another object of an embodiment of the present invention is to provide a power integrity analysis integration tool which is configured such that it can used by someone who is not an expert in running power integrity tools.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a power integrity analysis integration tool for analyzing the power integrity of a semiconductor layout previously designed using a separate design tool. The power integrity analysis integration tool provides a graphic user interface that is configured to extract layout data from the design tool and perform a transistor-level analysis of the power integrity of the semiconductor layout.
Preferably, the results of the analysis is displayed, and the power integrity analysis integration tool determines whether a correct environment was set up by a user using the design tool, logs all operations and collect all logs in a common place, checks for errors at each step of the analysis, performs batch queuing of all commands, saves all settings and retrieves the settings each time the power integrity analysis integration tool is started. Additionally, preferably the power integrity analysis integration tool is configured to interact with a plurality of different design tools, and is configured to determine which optimized binaries to use for each different design tool. Preferably, the power integrity analysis integration tool is configured such that a user selects which design tool is to be interacted with by the power integrity analysis integration tool. Preferably, the power integrity analysis integration tool is configured to prompt the user for a location of the data to be extracted, and is configured such that a plurality of procedures are listed to be selected by the user, and the power integrity analysis integration tool performs the selected procedures during the analysis. A method of designing a semiconductor layout and performing a transistor-level analysis of the power integrity of the semiconductor layout includes, first, using a design tool to design the semiconductor layout, and then using the power integrity analysis integration tool to extract layout data from the design tool and perform a transistor-level analysis of the power integrity of the semiconductor layout.